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| GTLP2T152 2-Bit LVTTL/GTLP Transceiver June 2001 Revised February 2002 GTLP2T152 2-Bit LVTTL/GTLP Transceiver General Description The GTLP2T152 is a 2-bit transceiver that provides LVTTLto-GTLP signal level translation. Data directional control is handled with a transmit/receive pin. High-speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus-settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transistor logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is process, voltage and temperature compensated. GTLP's I/O structure is similar to GTL and BTL but offers different output levels and receiver threshold. Typical GTLP output voltage levels are: VOL = 0.5V, VOH = 1.5V, and VREF = 1V. Features s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustibility s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible driver and control inputs s Designed using Fairchild advanced BiCMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s Open drain on GTLP to support wired-or connection s Flow through pinout optimizes PCB layout s A Port source/sink -24mA/+24mA s B Port sink +50mA Ordering Code: Order Number GTLP2T152M GTLP2T152MX GTLP2T152K8X Package Number Package Description M08A M08A MAB08A (Preliminary) 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TUBE] 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow [TAPE and REEL] 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide [TAPE and REEL] Pin Descriptions Pin Names T/R Description LVTTL Direction Control (Receive Direction is Active LOW) Connection Diagrams US8 VCC, GND, VREF Device Supplies An Bn A Port LVTTL Input/Output B Port GTLP Input/Output SOIC (c) 2002 Fairchild Semiconductor Corporation DS500486 www.fairchildsemi.com GTLP2T152 Functional Description The GTLP2T152 is a 2-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting and the the GTLP/LVTTL outputs are controlled by the T/R pin. Functional Table Inputs Outputs T/R H L Bus An Data to Bus Bn Bus Bn Data to Bus An Bn Output Data Enabled An Output Data Enabled Description Logic Diagram www.fairchildsemi.com 2 GTLP2T152 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V ESD Rating Storage Temperature (TSTG) 100 mA 48 mA -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V -0.5V to +4.6V Recommended Operating Conditions Supply Voltage VCC Bus Termination Voltage (VTT) GTLP VREF Input Voltage (VI) on A Port and Control Pins HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) 0.0V to VCC 1.47V to 1.53V 0.98V to 1.02V 3.15V to 3.45V -48 mA -24 mA +24 mA +50 mA -40C to +85C -50 mA -50 mA >2000V -65C to +150C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the "Electrical Characteristics" table are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL VREF VTT VIK VOH A Port B Port Others B Port Others B Port B Port VCC = 3.15V VCC = Min to Max (Note 4) VCC = 3.15V VOL A Port VCC = Min to Max (Note 4) VCC = 3.15V VCC = 3.15V B Port II Control Pins A Port B Port IOFF A Port, Control Pins B Port II (HOLD) IOZH A Port A Port B Port VCC = 0 VCC = 3.15V VCC = 3.45V VI or VO = 0 to 3.45V VI = 0.8V VI = 2.0V VO = 3.45V VO = 3.45V 75 -75 10 5 30 A VCC = 3.15V VCC = 3.45V VCC = 3.45V VCC = 3.45V VCC = 0 II = -18 mA IOH = -100 A IOH = -8 mA IOH = -24 mA IOL = 100 A IOL = 8 mA IOL = 24 mA IOL = 40 mA IOL = 50 mA VI = 3.45V VI = 0V VI = 3.45V VI = 0V VI = 3.45V VI = 0 VI or VO = 0 to 3.45V VCC - 0.2 2.4 2.2 0.2 0.4 0.5 0.4 0.55 5 -5 10 -10 5 -5 30 V A A A A V V 0.7V VREF + 50 mV 1.0 1.5 Test Conditions Min VREF + 0.05 2.0 0.0 VREF - 0.05 0.8 1.3V VCC -1.2 Typ (Note 3) VTT Max Units V V V V V A A 3 www.fairchildsemi.com GTLP2T152 DC Electrical Characteristics Symbol IOZL IPU/PD ICC A Port B Port All Ports A Port or B Port ICC (Note 5) Ci CI/O A Port and Control Pins Control Pins A Port B Port Note 3: All typical values are at VCC = 3.3V and TA = 25C. (Continued) Min Typ (Note 3) -10 -5 30 11 11 11 2 3 5 5.5 mA pF pF pF mA Max Test Conditions VCC = 3.45V VCC = 0 to 1.5V VCC = 3.45V IO = 0 VI = VCC/VTT or GND VCC = 3.45V, VO = 0V VO = 0V VI = 0 to 3.45V Outputs HIGH Outputs LOW Outputs Disabled One Input at VCC VI = VCC or 0 VI = VCC or 0 VI = VTT or 0 Units A A A or Control Inputs at VCC or GND -0.6V Note 4: For conditions shown as Min, use the appropriate value specified under recommended operating conditions. Note 5: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. Note: GTLP V REF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted beyond the recommended operating to accommodate backplane impedances other than 50, but must remain within the boundaries of the DC Absolute Maximum Ratings. Similarly, VREF can be adjusted to optimize noise margin. AC Electrical Characteristics Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port. Symbol tPLH tPHL tPLH tPHL tRISE tFALL tRISE tFALL From (Input) A B To (Output) B A 1.2 0.8 1.4 1.6 Min Typ (Note 6) 2.9 2.0 2.5 2.7 1.5 1.8 2.5 2.2 7.3 4.5 4.4 5.0 Max Unit ns ns ns ns ns ns Transition Time, B Outputs (20% to 80%) Transition Time, B Outputs (80% to 20%) Transition Time, A Outputs (10% to 90%) Transition Time, A Outputs (90% to 10%) Note 6: All typical values are at VCC = 3.3V, and TA = 25C. www.fairchildsemi.com 4 GTLP2T152 Test Circuits and Timing Waveforms Test Circuit for A Outputs Test Circuit for B Outputs Test tPLZ/tPZL S 6V Note: CL includes probes and Jig capacitance. Note: For B Port, CL = 30 pF is used for worst case. tPLH/tPHL OPEN tPHZ/tPZH GND Note: C L includes probes and Jig capacitance. Voltage Waveforms Propagation Delay Voltage Waveform Enable and Disable Times A or LVTTL Pins VINHIGH VINLOW VM VX VY VCC 0.0 VCC/2 VOL + 0.3V VOH - 0.3V B or GTLP Pins 1.5 0.0 1.0 N/A N/A Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Note: All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns (10% to 90%), ZO = 50. The outputs are measured one at a time with one transition per measurement. 5 www.fairchildsemi.com GTLP2T152 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 6 GTLP2T152 2-Bit LVTTL/GTLP Transceiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Package Number MAB08A Preliminary Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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